Geneve keyboard control - Revision history

Mizapf: /* Get a scancode */

2019-08-30T22:57:45Z

Get a scancode

← Older revision		Revision as of 22:57, 30 August 2019
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	Two subsequent scancodes arrive at a 1.3 ms interval which means a maximum rate of 768 scancodes per second, each one having 10 bits (2 start bits, 8 data bits), so that means 7680 bits/second. (Note that a keystroke requires at least two scancodes; one for press, one for release.) Key repetition occurs with about 42 ms intervals, i.e. 23.5 characters per second.		Two subsequent scancodes arrive at a 1.3 ms interval which means a maximum rate of 768 scancodes per second, each one having 10 bits (2 start bits, 8 data bits), so that means 7680 bits/second. (Note that a keystroke requires at least two scancodes; one for press, one for release.) Key repetition occurs with about 42 ms intervals, i.e. 23.5 characters per second.

	Another observation: When an interrupt has been raised, the ~~clock~~ line is ~~obviously pulled~~ down automatically. This can be seen with multi-code keys (E01D for right Ctrl): You can wait a long time after receiving a scancode, and the keyboard is ~~obviously~~ unable to continue sending.		Another observation: When an interrupt has been raised, the data line is held down automatically. This can be seen with multi-code keys (E01D for right Ctrl): You can wait a long time after receiving a scancode, and the keyboard is unable to continue sending.

	=== Initialize the keyboard ===		=== Initialize the keyboard ===

Mizapf: /* Control bit 1 */

2019-08-30T22:53:26Z

Control bit 1

← Older revision		Revision as of 22:53, 30 August 2019
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	=== Control bit 1 ===		=== Control bit 1 ===

	The bit at '''CRU address 1EF2''' ~~also~~ has two functions:		The bit at '''CRU address 1EF2''' has two functions:

	* ~~When set to 0 (~~SBZ~~), the~~ shift register is cleared~~, the~~ available flag is set to 1, and the ~~clock~~ line is ~~enabled. This means the keyboard will now begin to send its buffered scancodes~~. The shift register is ~~locked~~ to ~~0, and any incoming scancode will be lost~~.		* SBZ: The shift register is cleared and locked to 0. The available flag is reset (set to 1), the interrupt cleared, and the keyboard data line is released.
	* When ~~set to 1 (SBO)~~, the ~~shift register is set~~ to ~~receive. The next incoming~~ scancode ~~will be read into the shift register. Scancodes are transmitted~~ LSB first, so the shift register ~~is loaded from~~ the ~~left. When~~ the ~~complete scancode has been received~~, the available flag is set to 0, and the ~~clock line~~ is ~~disabled~~.
			* SBO: The shift register is set to receive.

			When the data line has been released, the keyboard starts to send the scancode (LSB first, with a leading 0 and a 1 (start bits)). When the shift register has received the full scancode, the data line is held low, while the available flag is asserted (set to 0) and the interrupt is triggered.

	Scancode reception is done in the background, without program control. The shift register will accept a scan code at any time after the SBO. This means that the shift register should be checked whether it contains a scancode that has been received in the meantime before setting the control bit 1 to 0, since this will wipe the shift register.		Scancode reception is done in the background, without program control. The shift register will accept a scan code at any time after the SBO. This means that the shift register should be checked whether it contains a scancode that has been received in the meantime before setting the control bit 1 to 0, since this will wipe the shift register.

Mizapf: /* Control bit 0 */

2019-08-30T22:31:20Z

Control bit 0

← Older revision		Revision as of 22:31, 30 August 2019
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	=== Control bit 0 ===		=== Control bit 0 ===

	The bit at '''CRU address 1EF0''' ~~has two functions:~~		The bit at '''CRU address 1EF0''' is directly routed to the keyboard clock line.

	* ~~When set to 0 (~~SBZ), the ~~keyboard clock is turned off~~. All following ~~keystrokes~~ are buffered in the keyboard ~~and are not propagated~~ to the ~~Gate Array~~.		Accordingly, setting and resetting the bit has the following effect:
	* When ~~set to 1 (SBO)~~, a reset ~~occurs (only if the previous state was 0; otherwise no effect)~~. This means the states of CapsLock, NumLock, and ScrollLock are set to off, the keyboard performs a self-test, clears the scancode buffer, and sends a AA code to the computer. ~~This scancode is~~ transmitted ~~as any other scancode~~, i.~~e. we have~~ to ~~check~~ the ~~available flag before getting it from~~ the ~~shift register~~.
			* SBZ: This pulls down the clock line, which disables the transfer of keycodes to the host. All following keycodes are buffered in the keyboard.

			* SBO: Setting the clock line to 1 allows the keyboard to strobe the line, thus transmitting the keycodes.

			There is another important effect: When the clock line is pulled down for more than 20 ms, the keyboard performs a reset. This means the states of CapsLock, NumLock, and ScrollLock are set to off, the keyboard performs a self-test, clears the scancode buffer, and sends a AA code to the computer. The AA code can only be transmitted after raising the clock line, so in order to properly reset the keyboard, we need to first set the line to 0, wait 20 ms, then raise to 1.

			It follows that this bit cannot be used to suspend the keyboard for a longer time, as the keyboard will do a reset after 20 ms.

	Control bit 0 can be changed in this way:		Control bit 0 can be changed in this way:

Mizapf: /* Get a scancode */

2019-08-29T23:47:43Z

Get a scancode

← Older revision		Revision as of 23:47, 29 August 2019
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	* Key releases have a separate scancode which is the key press code plus >80.		* Key releases have a separate scancode which is the key press code plus >80.

	Two subsequent scancodes arrive at a 1.3 ms interval which means a maximum rate of 768 scancodes per second, each one having 11 bits (1 start, 8 data~~, 1 parity, 1 stop~~), so that means ~~8448~~ bits/second. (Note that a keystroke requires at least two scancodes; one for press, one for release.) ~~Adding some processing overhead this yields a connection rate of 9600 baud.~~ Key repetition occurs with about 42 ms intervals, i.e. 23.5 characters per second.		Two subsequent scancodes arrive at a 1.3 ms interval which means a maximum rate of 768 scancodes per second, each one having 10 bits (2 start bits, 8 data bits), so that means 7680 bits/second. (Note that a keystroke requires at least two scancodes; one for press, one for release.) Key repetition occurs with about 42 ms intervals, i.e. 23.5 characters per second.

			Another observation: When an interrupt has been raised, the clock line is obviously pulled down automatically. This can be seen with multi-code keys (E01D for right Ctrl): You can wait a long time after receiving a scancode, and the keyboard is obviously unable to continue sending.

	=== Initialize the keyboard ===		=== Initialize the keyboard ===

Mizapf at 14:30, 17 July 2016

2016-07-17T14:30:34Z

@@ Line 1: / Line 1: @@
 The Geneve uses a MF1 keyboard (PC-XT). Access to the keyboard is implemented as follows:
-== Keyboard interface ==
+== XOP interface in GeneveOS ==
 === Shift register ===

Mizapf: /* Available flag */

2011-11-10T11:42:22Z

Available flag

← Older revision		Revision as of 11:42, 10 November 2011
Line 15:		Line 15:
	It is set to 0 when a scancode is available in the shift register at F118. The input is configured to raise an interrupt which will make MDOS read the scancode and put it in a buffer, unless interrupts are masked out (using LIMI).		It is set to 0 when a scancode is available in the shift register at F118. The input is configured to raise an interrupt which will make MDOS read the scancode and put it in a buffer, unless interrupts are masked out (using LIMI).

	The bit is reset to 1 with the next SBZ on the control bit 1.		The bit is reset to 1 with the next SBZ on the control bit 1.

			Use the TB command to get the value:

			CLR R12
			TB 8
			JEQ NONE
			JNE GOTIT

			The Equal bit is set to the value of the CRU bit, so when the bit is 1, EQ is set to one.

	=== Control bit 0 ===		=== Control bit 0 ===

Mizapf: /* Control bit 1 */

2011-11-10T11:40:14Z

Control bit 1

← Older revision		Revision as of 11:40, 10 November 2011
Line 46:		Line 46:

	Scancode reception is done in the background, without program control. The shift register will accept a scan code at any time after the SBO. This means that the shift register should be checked whether it contains a scancode that has been received in the meantime before setting the control bit 1 to 0, since this will wipe the shift register.		Scancode reception is done in the background, without program control. The shift register will accept a scan code at any time after the SBO. This means that the shift register should be checked whether it contains a scancode that has been received in the meantime before setting the control bit 1 to 0, since this will wipe the shift register.

			Control bit 1 can be changed in this way:

			LI R12,>1EF0
			SBO 1
			LI R12,>1EE0
			SBZ 9

	== Writing a keyboard driver ==		== Writing a keyboard driver ==

Mizapf: /* Control bit 0 */

2011-11-10T11:39:22Z

Control bit 0

@@ Line 23: / Line 23: @@
 * When set to 0 (SBZ), the keyboard clock is turned off. All following keystrokes are buffered in the keyboard and are not propagated to the Gate Array.
 * When set to 1 (SBO), a reset occurs (only if the previous state was 0; otherwise no effect). This means the states of CapsLock, NumLock, and ScrollLock are set to off, the keyboard performs a self-test, clears the scancode buffer, and sends a AA code to the computer. This scancode is transmitted as any other scancode, i.e. we have to check the available flag before getting it from the shift register.
 === Control bit 1 ===

Mizapf: /* Initialize the keyboard */

2011-11-10T11:36:15Z

Initialize the keyboard

← Older revision		Revision as of 11:36, 10 November 2011
Line 77:		Line 77:

	This is quite similar to the above. The SBO 9 line is not required if we are sure that the last operation on the control bit was not a SBZ. The normal case, as shown above, is to set the control bit to 0 only for short, directly followed by a SBO. If you replace the SBO 9 by a SBZ 9, the shift register will not be loaded with the return code.		This is quite similar to the above. The SBO 9 line is not required if we are sure that the last operation on the control bit was not a SBZ. The normal case, as shown above, is to set the control bit to 0 only for short, directly followed by a SBO. If you replace the SBO 9 by a SBZ 9, the shift register will not be loaded with the return code.

			Experiments showed that between the SBZ and the SBO a minimum delay time of around 0.17 ms should pass (about 500 cycles), or no reset will occur.

			Another thing to consider is that there should be no intermediate scancodes (possibly from key releases). Before the SBZ one should try to poll remaining scancodes from the keyboard.

	[[Category:Geneve]]		[[Category:Geneve]]
	[[Category:MDOS]]		[[Category:MDOS]]

Mizapf: /* Control bit 0 */

2011-11-10T11:35:51Z

Control bit 0

← Older revision		Revision as of 11:35, 10 November 2011
Line 23:		Line 23:
	* When set to 0 (SBZ), the keyboard clock is turned off. All following keystrokes are buffered in the keyboard and are not propagated to the Gate Array.		* When set to 0 (SBZ), the keyboard clock is turned off. All following keystrokes are buffered in the keyboard and are not propagated to the Gate Array.
	* When set to 1 (SBO), a reset occurs (only if the previous state was 0; otherwise no effect). This means the states of CapsLock, NumLock, and ScrollLock are set to off, the keyboard performs a self-test, clears the scancode buffer, and sends a AA code to the computer. This scancode is transmitted as any other scancode, i.e. we have to check the available flag before getting it from the shift register.		* When set to 1 (SBO), a reset occurs (only if the previous state was 0; otherwise no effect). This means the states of CapsLock, NumLock, and ScrollLock are set to off, the keyboard performs a self-test, clears the scancode buffer, and sends a AA code to the computer. This scancode is transmitted as any other scancode, i.e. we have to check the available flag before getting it from the shift register.

	~~Experiments showed that between the SBZ and the SBO a minimum delay time of around 0.17 ms should pass (about 500 cycles), or no reset will occur.~~

	~~Another thing to consider is that there should be no intermediate scancodes (possibly from key releases). Before the SBZ one should try to poll remaining scancodes from the keyboard.~~

	=== Control bit 1 ===		=== Control bit 1 ===