Geneve physical memory map - Revision history

Mizapf: /* Memory map */

2024-06-02T12:15:12Z

Memory map

← Older revision		Revision as of 12:15, 2 June 2024
Line 112:		Line 112:
	\| class="bank" \| C0-E7		\| class="bank" \| C0-E7
	\| class="b64" \| Future SRAM expansion		\| class="b64" \| Future SRAM expansion
	\| class="descr" \| ~~Only in P~~-~~Box~~		\| class="descr" \| On-board, but with 1 WS
	\|-		\|-
	! 1D0000		! 1D0000

Mizapf: /* Memory map */

2024-06-02T12:14:40Z

Memory map

← Older revision		Revision as of 12:14, 2 June 2024
Line 34:		Line 34:
	\| class="bank" \| C0-E7		\| class="bank" \| C0-E7
	\| class="b64" \| Future SRAM expansion		\| class="b64" \| Future SRAM expansion
	\| class="descr" \| ~~Only in P~~-~~Box~~		\| class="descr" \| On-board, but with 1 WS
	\|-		\|-
	! 1D0000		! 1D0000

Stefan Haubenthal: Category

2023-07-13T12:45:58Z

Mizapf: Change bank -> page

2021-01-28T21:04:35Z

Change bank -> page

← Older revision		Revision as of 21:04, 28 January 2021
Line 7:		Line 7:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!
Line 54:		Line 54:
	=== Memory expansions ===		=== Memory expansions ===

	The ~~bank~~ area 40-7F is assigned to a "Future on-board memory expansion". In fact, the external bus (to the PEB) is not activated during accesses in that area, which means that external cards cannot populate this space. However, the Geneve main board does not offer sockets for such additional on-board memory. It is not possible to add these chips on top of the existing DRAM chips either. The only way to make use of this area is by using the MEMEX in a Genmod configuration.		The page area 40-7F is assigned to a "Future on-board memory expansion". In fact, the external bus (to the PEB) is not activated during accesses in that area, which means that external cards cannot populate this space. However, the Geneve main board does not offer sockets for such additional on-board memory. It is not possible to add these chips on top of the existing DRAM chips either. The only way to make use of this area is by using the MEMEX in a Genmod configuration.

	The ~~bank~~ area C0-E7 is assigned to SRAM (0 ws) fast memory. For accesses in that area, the external bus is activated, which means that SRAM chips for that area must be put on a card that plugs into the PEB.		The page area C0-E7 is assigned to SRAM (0 ws) fast memory. For accesses in that area, the external bus is activated, which means that SRAM chips for that area must be put on a card that plugs into the PEB.

	=== Boot EPROM space ===		=== Boot EPROM space ===

	The Boot EPROM region may have up to 128 KiB space as 16 ~~banks~~ of 8 KiB. This is used with the [[Programmable Flash Memory Expansion \| PFM]].		The Boot EPROM region may have up to 128 KiB space as 16 pages of 8 KiB. This is used with the [[Programmable Flash Memory Expansion \| PFM]].

	On reset, ~~bank~~ F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even ~~banks~~ as mirrors of F0, and all odd ~~banks~~ as mirrors of F1.		On reset, page F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even pages as mirrors of F0, and all odd pages as mirrors of F1.

	== GPL mode ==		== GPL mode ==
Line 70:		Line 70:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!
Line 135:		Line 135:

	* The mapper byte 06 (F116 / 8006) must be set to 03 to enable the GROM/GRAM cartridge space. Otherwise, no GROM/GRAM handling is emulated.		* The mapper byte 06 (F116 / 8006) must be set to 03 to enable the GROM/GRAM cartridge space. Otherwise, no GROM/GRAM handling is emulated.
	* In GPL mode, logical addresses 6000-7FFF are always mapped to ~~bank~~ 36/37, regardless of the mapper byte 03 (F113 / 8003).		* In GPL mode, logical addresses 6000-7FFF are always mapped to page 36/37, regardless of the mapper byte 03 (F113 / 8003).
	* CRU address 1EF8 is used to switch between single or dual bank cartridge ROM. When set to 0, only ~~bank~~ 36 is used. When set to 1, writing to cartridge space addresses 6000 + n4 selects ~~bank~~ 36, while writing to 6002 + n4 selects ~~bank~~ 37.		* CRU address 1EF8 is used to switch between single or dual bank cartridge ROM. When set to 0, only page 36 is used. When set to 1, writing to cartridge space addresses 6000 + n4 selects page 36, while writing to 6002 + n4 selects page 37.
	* Cartridge GRAM regions are 8 KiB large, unlike real GROMs with 6 KiB.		* Cartridge GRAM regions are 8 KiB large, unlike real GROMs with 6 KiB.
	* Address wrapping occurs at 8K boundaries (3FFF+1 = 2000).		* Address wrapping occurs at 8K boundaries (3FFF+1 = 2000).
Line 150:		Line 150:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!
Line 189:		Line 189:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!

Mizapf at 13:14, 27 January 2021

2021-01-27T13:14:40Z

← Older revision		Revision as of 13:14, 27 January 2021
Line 60:		Line 60:
	=== Boot EPROM space ===		=== Boot EPROM space ===

	The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the [[PFM]].		The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the [[Programmable Flash Memory Expansion \| PFM]].

	On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.		On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.

Mizapf: /* Genmod */

2021-01-27T13:10:42Z

Genmod

← Older revision		Revision as of 13:10, 27 January 2021
Line 176:		Line 176:
	! 080000		! 080000
	\| class="bank" \| 40-EF		\| class="bank" \| 40-EF
	\| class="~~sramb~~" \| 1408 KiB P-Box memory expansion (MEMEX)		\| class="sraml" \| 1408 KiB P-Box memory expansion (MEMEX)
	\| class="descr" \| SRAM (0 ws)		\| class="descr" \| SRAM (0 ws)
	\|-		\|-
	! 1E0000		! 1E0000
	\| class="bank" \| F0-FF		\| class="bank" \| F0-FF
	\| 128 KiB Boot EPROM		\| class="b128" \| 128 KiB Boot EPROM
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}
Line 195:		Line 195:
	! 000000		! 000000
	\| class="bank" \| 00-EF		\| class="bank" \| 00-EF
	\| class="~~sramb~~" \| 1920 P-Box memory expansion (MEMEX)		\| class="sraml" \| 1920 KiB P-Box memory expansion (MEMEX)
	\| class="descr" \| SRAM (0 ws)		\| class="descr" \| SRAM (0 ws)
	\|-		\|-
	! 1E0000		! 1E0000
	\| class="bank" \| F0-FF		\| class="bank" \| F0-FF
	\| 128 KiB Boot EPROM		\| class="b128" \| 128 KiB Boot EPROM
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}

Mizapf: /* Memory map */

2021-01-27T13:08:56Z

Memory map

← Older revision		Revision as of 13:08, 27 January 2021
Line 96:		Line 96:
	! 080000		! 080000
	\| class="bank" \| 40-7F		\| class="bank" \| 40-7F
	\| 512 KiB On-board DRAM expansion		\| class="b512" \| 512 KiB On-board DRAM expansion
	\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)		\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)
	\|-		\|-
	! 100000		! 100000
	\| class="bank" \| 80-B7		\| class="bank" \| 80-B7
	\| 448 KiB P-Box space		\| class="b128" \| 448 KiB P-Box space
	\| class="descr" \| May be used by MEMEX card		\| class="descr" \| May be used by MEMEX card
	\|-		\|-
	! 170000		! 170000
	\| class="bank" \| B8-BF		\| class="bank" \| B8-BF
	\| 64 KiB P-Box space		\| class="b64" \| 64 KiB P-Box space
	\| class="descr" \| Used by current expansion cards		\| class="descr" \| Used by current expansion cards
	\|-		\|-
	! 180000		! 180000
	\| class="bank" \| C0-E7		\| class="bank" \| C0-E7
	\| class="~~sram~~" \| Future SRAM expansion		\| class="b64" \| Future SRAM expansion
	\| class="descr" \| Only in P-Box		\| class="descr" \| Only in P-Box
	\|-		\|-
	! 1D0000		! 1D0000
	\| class="bank" \| E8-EB		\| class="bank" \| E8-EB
	\| class="~~sramb~~" \| 32 KiB On-board SRAM expansion		\| class="sram" \| 32 KiB On-board SRAM expansion
	\| class="descr" \| Soldered on top of the existing 32 KiB chip		\| class="descr" \| Soldered on top of the existing 32 KiB chip
	\|-		\|-
	! 1D8000		! 1D8000
	\| class="bank" \| EC-EF		\| class="bank" \| EC-EF
	\| class="~~sramb~~" \| 32 KiB On-board SRAM		\| class="sram" \| 32 KiB On-board SRAM
	\| class="descr" \| Original SRAM memory (0 ws)		\| class="descr" \| Original SRAM memory (0 ws)
	\|-		\|-
	! 1E0000		! 1E0000
	\| class="bank" \| F0-FF		\| class="bank" \| F0-FF
	\| 128 KiB Boot EPROM		\| class="b128" \| 128 KiB Boot EPROM
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}

Mizapf: /* Native mode */

2021-01-27T13:04:56Z

Native mode

← Older revision		Revision as of 13:04, 27 January 2021
Line 18:		Line 18:
	! 080000		! 080000
	\| class="bank" \| 40-7F		\| class="bank" \| 40-7F
	\| 512 KiB On-board DRAM expansion		\| class="b512" \| 512 KiB On-board DRAM expansion
	\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)		\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)
	\|-		\|-
	! 100000		! 100000
	\| class="bank" \| 80-B7		\| class="bank" \| 80-B7
	\| 448 KiB P-Box space		\| class="b64" \| 448 KiB P-Box space
	\| class="descr" \| May be used by MEMEX card		\| class="descr" \| May be used by MEMEX card
	\|-		\|-
	! 170000		! 170000
	\| class="bank" \| B8-BF		\| class="bank" \| B8-BF
	\| 64 KiB P-Box space		\| class="b64" \| 64 KiB P-Box space
	\| class="descr" \| Used by current expansion cards		\| class="descr" \| Used by current expansion cards
	\|-		\|-
	! 180000		! 180000
	\| class="bank" \| C0-E7		\| class="bank" \| C0-E7
	\| class="~~sram~~" \| Future SRAM expansion		\| class="b64" \| Future SRAM expansion
	\| class="descr" \| Only in P-Box		\| class="descr" \| Only in P-Box
	\|-		\|-
	! 1D0000		! 1D0000
	\| class="bank" \| E8-EB		\| class="bank" \| E8-EB
	\| class="~~sramb~~" \| 32 KiB On-board SRAM expansion		\| class="sram" \| 32 KiB On-board SRAM expansion
	\| class="descr" \| Soldered on top of the existing 32 KiB chip		\| class="descr" \| Soldered on top of the existing 32 KiB chip
	\|-		\|-
	! 1D8000		! 1D8000
	\| class="bank" \| EC-EF		\| class="bank" \| EC-EF
	\| class="~~sramb~~" \| 32 KiB On-board SRAM		\| class="sram" \| 32 KiB On-board SRAM
	\| class="descr" \| Original SRAM memory (0 ws)		\| class="descr" \| Original SRAM memory (0 ws)
	\|-		\|-
	! 1E0000		! 1E0000
	\| class="bank" \| F0-FF		\| class="bank" \| F0-FF
	\| 128 KiB Boot EPROM		\| class="b128" \| 128 KiB Boot EPROM
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}

Mizapf at 12:57, 27 January 2021

2021-01-27T12:57:44Z

← Older revision		Revision as of 12:57, 27 January 2021
Line 24:		Line 24:
	\| class="bank" \| 80-B7		\| class="bank" \| 80-B7
	\| 448 KiB P-Box space		\| 448 KiB P-Box space
	\| class="descr" \| May be used my MEMEX card		\| class="descr" \| May be used by MEMEX card
	\|-		\|-
	! 170000		! 170000
Line 38:		Line 38:
	! 1D0000		! 1D0000
	\| class="bank" \| E8-EB		\| class="bank" \| E8-EB
	\| class="~~sram~~" \| 32 KiB On-board SRAM expansion		\| class="sramb" \| 32 KiB On-board SRAM expansion
	\| class="descr" \| Soldered on top of the existing 32 KiB chip		\| class="descr" \| Soldered on top of the existing 32 KiB chip
	\|-		\|-
	! 1D8000		! 1D8000
	\| class="bank" \| EC-EF		\| class="bank" \| EC-EF
	\| class="~~sram~~" \| 32 KiB On-board SRAM		\| class="sramb" \| 32 KiB On-board SRAM
	\| class="descr" \| Original SRAM memory (0 ws)		\| class="descr" \| Original SRAM memory (0 ws)
	\|-		\|-
Line 76:		Line 76:
	! 000000		! 000000
	\| class="bank" \| 00-35		\| class="bank" \| 00-35
	\| class="~~dram~~" \| 432 KiB On-board DRAM		\| class="dramb" \| 432 KiB On-board DRAM
	\| class="descr" \| Slow RAM (1 ws)		\| class="descr" \| Slow RAM (1 ws)
	\|-		\|-
Line 116:		Line 116:
	! 1D0000		! 1D0000
	\| class="bank" \| E8-EB		\| class="bank" \| E8-EB
	\| class="~~sram~~" \| 32 KiB On-board SRAM expansion		\| class="sramb" \| 32 KiB On-board SRAM expansion
	\| class="descr" \| Soldered on top of the existing 32 KiB chip		\| class="descr" \| Soldered on top of the existing 32 KiB chip
	\|-		\|-
	! 1D8000		! 1D8000
	\| class="bank" \| EC-EF		\| class="bank" \| EC-EF
	\| class="~~sram~~" \| 32 KiB On-board SRAM		\| class="sramb" \| 32 KiB On-board SRAM
	\| class="descr" \| Original SRAM memory (0 ws)		\| class="descr" \| Original SRAM memory (0 ws)
	\|-		\|-
Line 156:		Line 156:
	! 000000		! 000000
	\| class="bank" \| 00-35		\| class="bank" \| 00-35
	\| class="~~dram~~" \| 432 KiB On-board DRAM		\| class="dramb" \| 432 KiB On-board DRAM
	\| class="descr" \| Slow RAM (1 ws)		\| class="descr" \| Slow RAM (1 ws)
	\|-		\|-
Line 176:		Line 176:
	! 080000		! 080000
	\| class="bank" \| 40-EF		\| class="bank" \| 40-EF
	\| class="~~sram~~" \| 1408 KiB P-Box memory expansion (MEMEX)		\| class="sramb" \| 1408 KiB P-Box memory expansion (MEMEX)
	\| class="descr" \| SRAM (0 ws)		\| class="descr" \| SRAM (0 ws)
	\|-		\|-
Line 195:		Line 195:
	! 000000		! 000000
	\| class="bank" \| 00-EF		\| class="bank" \| 00-EF
	\| class="~~sram~~" \| 1920 P-Box memory expansion (MEMEX)		\| class="sramb" \| 1920 P-Box memory expansion (MEMEX)
	\| class="descr" \| SRAM (0 ws)		\| class="descr" \| SRAM (0 ws)
	\|-		\|-

Mizapf: /* Native mode */

2021-01-27T12:55:18Z

Native mode

← Older revision		Revision as of 12:55, 27 January 2021
Line 13:		Line 13:
	! 000000		! 000000
	\| class="bank" \| 00-3F		\| class="bank" \| 00-3F
	\| class="~~dram~~" \| 512 KiB On-board DRAM		\| class="dramb" \| 512 KiB On-board DRAM
	\| class="descr" \| Slow RAM (1 ws)		\| class="descr" \| Slow RAM (1 ws)
	\|-		\|-

← Older revision		Revision as of 12:45, 13 July 2023
Line 203:		Line 203:
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}

			[[Category:Geneve]]

← Older revision		Revision as of 21:04, 28 January 2021
Line 7:		Line 7:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!
Line 54:		Line 54:
	=== Memory expansions ===		=== Memory expansions ===

	The ~~bank~~ area 40-7F is assigned to a "Future on-board memory expansion". In fact, the external bus (to the PEB) is not activated during accesses in that area, which means that external cards cannot populate this space. However, the Geneve main board does not offer sockets for such additional on-board memory. It is not possible to add these chips on top of the existing DRAM chips either. The only way to make use of this area is by using the MEMEX in a Genmod configuration.		The page area 40-7F is assigned to a "Future on-board memory expansion". In fact, the external bus (to the PEB) is not activated during accesses in that area, which means that external cards cannot populate this space. However, the Geneve main board does not offer sockets for such additional on-board memory. It is not possible to add these chips on top of the existing DRAM chips either. The only way to make use of this area is by using the MEMEX in a Genmod configuration.

	The ~~bank~~ area C0-E7 is assigned to SRAM (0 ws) fast memory. For accesses in that area, the external bus is activated, which means that SRAM chips for that area must be put on a card that plugs into the PEB.		The page area C0-E7 is assigned to SRAM (0 ws) fast memory. For accesses in that area, the external bus is activated, which means that SRAM chips for that area must be put on a card that plugs into the PEB.

	=== Boot EPROM space ===		=== Boot EPROM space ===

	The Boot EPROM region may have up to 128 KiB space as 16 ~~banks~~ of 8 KiB. This is used with the [[Programmable Flash Memory Expansion \| PFM]].		The Boot EPROM region may have up to 128 KiB space as 16 pages of 8 KiB. This is used with the [[Programmable Flash Memory Expansion \| PFM]].

	On reset, ~~bank~~ F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even ~~banks~~ as mirrors of F0, and all odd ~~banks~~ as mirrors of F1.		On reset, page F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even pages as mirrors of F0, and all odd pages as mirrors of F1.

	== GPL mode ==		== GPL mode ==
Line 70:		Line 70:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!
Line 135:		Line 135:

	* The mapper byte 06 (F116 / 8006) must be set to 03 to enable the GROM/GRAM cartridge space. Otherwise, no GROM/GRAM handling is emulated.		* The mapper byte 06 (F116 / 8006) must be set to 03 to enable the GROM/GRAM cartridge space. Otherwise, no GROM/GRAM handling is emulated.
	* In GPL mode, logical addresses 6000-7FFF are always mapped to ~~bank~~ 36/37, regardless of the mapper byte 03 (F113 / 8003).		* In GPL mode, logical addresses 6000-7FFF are always mapped to page 36/37, regardless of the mapper byte 03 (F113 / 8003).
	* CRU address 1EF8 is used to switch between single or dual bank cartridge ROM. When set to 0, only ~~bank~~ 36 is used. When set to 1, writing to cartridge space addresses 6000 + n4 selects ~~bank~~ 36, while writing to 6002 + n4 selects ~~bank~~ 37.		* CRU address 1EF8 is used to switch between single or dual bank cartridge ROM. When set to 0, only page 36 is used. When set to 1, writing to cartridge space addresses 6000 + n4 selects page 36, while writing to 6002 + n4 selects page 37.
	* Cartridge GRAM regions are 8 KiB large, unlike real GROMs with 6 KiB.		* Cartridge GRAM regions are 8 KiB large, unlike real GROMs with 6 KiB.
	* Address wrapping occurs at 8K boundaries (3FFF+1 = 2000).		* Address wrapping occurs at 8K boundaries (3FFF+1 = 2000).
Line 150:		Line 150:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!
Line 189:		Line 189:
	{\| class="memory"		{\| class="memory"
	! class="top" \| Address		! class="top" \| Address
	! class="top" \| ~~Banks~~		! class="top" \| Pages
	! class="top" \| Region		! class="top" \| Region
	!		!

← Older revision		Revision as of 13:08, 27 January 2021
Line 96:		Line 96:
	! 080000		! 080000
	\| class="bank" \| 40-7F		\| class="bank" \| 40-7F
	\| 512 KiB On-board DRAM expansion		\| class="b512" \| 512 KiB On-board DRAM expansion
	\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)		\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)
	\|-		\|-
	! 100000		! 100000
	\| class="bank" \| 80-B7		\| class="bank" \| 80-B7
	\| 448 KiB P-Box space		\| class="b128" \| 448 KiB P-Box space
	\| class="descr" \| May be used by MEMEX card		\| class="descr" \| May be used by MEMEX card
	\|-		\|-
	! 170000		! 170000
	\| class="bank" \| B8-BF		\| class="bank" \| B8-BF
	\| 64 KiB P-Box space		\| class="b64" \| 64 KiB P-Box space
	\| class="descr" \| Used by current expansion cards		\| class="descr" \| Used by current expansion cards
	\|-		\|-
	! 180000		! 180000
	\| class="bank" \| C0-E7		\| class="bank" \| C0-E7
	\| class="~~sram~~" \| Future SRAM expansion		\| class="b64" \| Future SRAM expansion
	\| class="descr" \| Only in P-Box		\| class="descr" \| Only in P-Box
	\|-		\|-
	! 1D0000		! 1D0000
	\| class="bank" \| E8-EB		\| class="bank" \| E8-EB
	\| class="~~sramb~~" \| 32 KiB On-board SRAM expansion		\| class="sram" \| 32 KiB On-board SRAM expansion
	\| class="descr" \| Soldered on top of the existing 32 KiB chip		\| class="descr" \| Soldered on top of the existing 32 KiB chip
	\|-		\|-
	! 1D8000		! 1D8000
	\| class="bank" \| EC-EF		\| class="bank" \| EC-EF
	\| class="~~sramb~~" \| 32 KiB On-board SRAM		\| class="sram" \| 32 KiB On-board SRAM
	\| class="descr" \| Original SRAM memory (0 ws)		\| class="descr" \| Original SRAM memory (0 ws)
	\|-		\|-
	! 1E0000		! 1E0000
	\| class="bank" \| F0-FF		\| class="bank" \| F0-FF
	\| 128 KiB Boot EPROM		\| class="b128" \| 128 KiB Boot EPROM
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}

← Older revision		Revision as of 13:04, 27 January 2021
Line 18:		Line 18:
	! 080000		! 080000
	\| class="bank" \| 40-7F		\| class="bank" \| 40-7F
	\| 512 KiB On-board DRAM expansion		\| class="b512" \| 512 KiB On-board DRAM expansion
	\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)		\| class="descr" \| Allocated, but technically infeasible (no sockets or signal lines)
	\|-		\|-
	! 100000		! 100000
	\| class="bank" \| 80-B7		\| class="bank" \| 80-B7
	\| 448 KiB P-Box space		\| class="b64" \| 448 KiB P-Box space
	\| class="descr" \| May be used by MEMEX card		\| class="descr" \| May be used by MEMEX card
	\|-		\|-
	! 170000		! 170000
	\| class="bank" \| B8-BF		\| class="bank" \| B8-BF
	\| 64 KiB P-Box space		\| class="b64" \| 64 KiB P-Box space
	\| class="descr" \| Used by current expansion cards		\| class="descr" \| Used by current expansion cards
	\|-		\|-
	! 180000		! 180000
	\| class="bank" \| C0-E7		\| class="bank" \| C0-E7
	\| class="~~sram~~" \| Future SRAM expansion		\| class="b64" \| Future SRAM expansion
	\| class="descr" \| Only in P-Box		\| class="descr" \| Only in P-Box
	\|-		\|-
	! 1D0000		! 1D0000
	\| class="bank" \| E8-EB		\| class="bank" \| E8-EB
	\| class="~~sramb~~" \| 32 KiB On-board SRAM expansion		\| class="sram" \| 32 KiB On-board SRAM expansion
	\| class="descr" \| Soldered on top of the existing 32 KiB chip		\| class="descr" \| Soldered on top of the existing 32 KiB chip
	\|-		\|-
	! 1D8000		! 1D8000
	\| class="bank" \| EC-EF		\| class="bank" \| EC-EF
	\| class="~~sramb~~" \| 32 KiB On-board SRAM		\| class="sram" \| 32 KiB On-board SRAM
	\| class="descr" \| Original SRAM memory (0 ws)		\| class="descr" \| Original SRAM memory (0 ws)
	\|-		\|-
	! 1E0000		! 1E0000
	\| class="bank" \| F0-FF		\| class="bank" \| F0-FF
	\| 128 KiB Boot EPROM		\| class="b128" \| 128 KiB Boot EPROM
	\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored		\| class="descr" \| Originally, only 16 KiB installed at F0,F1; mirrored
	\|}		\|}