Programmable Systems Interface TMS 9901 - Revision history

Mizapf at 12:04, 24 April 2022

2022-04-24T12:04:51Z

← Older revision		Revision as of 12:04, 24 April 2022
Line 60:		Line 60:
	Note that the CRU base address in R12 advances in steps of 2, so bit 16 is on address 32. Also, for reading 16 bits, you must specify a count of 0.		Note that the CRU base address in R12 advances in steps of 2, so bit 16 is on address 32. Also, for reading 16 bits, you must specify a count of 0.

	~~The 9901 offers some more inputs than~~ the 16 ports~~; we can use~~ the interrupt inputs as well. More about that can be found in the section about the [[#Interrupt_mode\| interrupt mode]].		Besides the 16 ports, the interrupt inputs of the 9901 can be used as input ports as well. More about that can be found in the section about the [[#Interrupt_mode\| interrupt mode]].

	=== Px port as output ===		=== Px port as output ===
Line 92:		Line 92:
	[[File:Int9901.png\|600px]]		[[File:Int9901.png\|600px]]

	This illustration is slightly simplified; there is a latch between each interrupt input and the mask AND gate. This is not relevant for our programming, though. For more details see the ~~[[#ref2 \|~~ TMS 9901 Programmable Systems Interface Data Manual]].		This illustration is slightly simplified; there is a latch between each interrupt input and the mask AND gate. This is not relevant for our programming, though. For more details see the ''TMS 9901 Programmable Systems Interface Data Manual'' [[#ref2\|[1]]].

	=== Checking the interrupt inputs ===		=== Checking the interrupt inputs ===
Line 113:		Line 113:
	=== Interrupt levels ===		=== Interrupt levels ===

	Each interrupt input (/INT1 to /INT15) may be used to trigger an interrupt at another circuit, typically the CPU. For this purpose, the ~~PSI~~ offers an /INTREQ outgoing line. In the TI console, it is routed to the /INTREQ input of the TMS9900 CPU.		Each interrupt input (/INT1 to /INT15) may be used to trigger an interrupt at another circuit, typically the CPU. For this purpose, the 9901 offers an /INTREQ outgoing line. In the TI console, it is routed to the /INTREQ input of the TMS9900 CPU.

	In addition there is a priority encoder, which is not shown here. This encoder outputs a 4-bit number which reflects the smallest number of the interrupt inputs where an interrupt has been sensed.		In addition there is a priority encoder, which is not shown here. This encoder outputs a 4-bit number which reflects the smallest number of the interrupt inputs where an interrupt has been sensed.
Line 146:		Line 146:
	Consequently, you '''cannot''' read the current mask setting of the 9901. What you get from reading are the input levels of the pins. So if you plan to change the mask bits temporarily, be aware that you cannot ask the 9901 to give you the current setting which you want to restore later. You will have to find out by another way.		Consequently, you '''cannot''' read the current mask setting of the 9901. What you get from reading are the input levels of the pins. So if you plan to change the mask bits temporarily, be aware that you cannot ask the 9901 to give you the current setting which you want to restore later. You will have to find out by another way.

	== ~~Counter~~ mode ==		== Clock mode ==

	Besides the I/O capabilities, the ~~PSI~~ offers a "real-time" clock. This should not be understood as a precise timer with seconds, hundreds of seconds or other but as a countdown timer that is decremented every 64 CPU clock cycles.		Besides the I/O capabilities, the 9901 offers a "real-time" clock. This should not be understood as a precise timer with seconds, hundreds of seconds or other but as a countdown timer that is decremented every 64 CPU clock cycles.

	This schematic is taken from the [[#ref1 \|~~Osborne book~~]], redrawn by me in LibreOffice (and with added Load Buffer).		This schematic is taken from the Osborne book [[#ref1 \|[2]]], redrawn by me in LibreOffice (and with added Load Buffer).

	[[File:Clock9901.png\|550px]]		[[File:Clock9901.png\|550px]]
Line 158:		Line 158:
	There are basically two ways of using the countdown timer:		There are basically two ways of using the countdown timer:

	* Interval timer: Set the counter to a value; wait until the counter reaches zero. The ~~PSI~~ can be set up to raise an interrupt at that instant.		* Interval timer: Set the counter to a value; wait until the counter reaches zero. The 9901 can be set up to raise an interrupt at that instant.
	* Event timer: Set the counter to a value; do something and then read the counter value.		* Event timer: Set the counter to a value; do something and then read the counter value.

Line 169:		Line 169:
	=== Setting the timer ===		=== Setting the timer ===

	In order to set the load buffer and so to define the maximum counter value, we must switch to clock mode. This is ~~achieved~~ by setting bit 0 of the ~~PSI~~ to 1. In the TI/Geneve systems, the ~~PSI~~ is mapped to CRU base address 0, so we can do this		In order to set the load buffer and so to define the maximum counter value, we must switch to clock mode. This is done by setting bit 0 of the 9901 to 1. In the TI/Geneve systems, the 9901 is mapped to CRU base address 0, so we can do this

	CLR R12		CLR R12
Line 192:		Line 192:
	LDCR R1,15		LDCR R1,15

	Do '''not''' write all 16 bits. The last bit will change bit 15 of the ~~PSI~~, which is the /RST2 bit. When we are in clock mode, writing a 0 to the /RST2 bit resets all I/O ports. This means that all pins are set to inputs, and devices that rely on them as outputs may be turned off unintentionally.		Do '''not''' write all 16 bits. The last bit will change bit 15 of the 9901, which is the /RST2 bit. When we are in clock mode, writing a 0 to the /RST2 bit resets all I/O ports. This means that all pins are set to inputs, and devices that rely on them as outputs may be turned off unintentionally.

	=== Reading the timer ===		=== Reading the timer ===
Line 200:		Line 200:
	For this reason, the timer value is copied to a '''read buffer'''. This happens at every 64th clock cycle, when the counter is also decremented, but only when we are '''not''' in clock mode.		For this reason, the timer value is copied to a '''read buffer'''. This happens at every 64th clock cycle, when the counter is also decremented, but only when we are '''not''' in clock mode.

	To read the buffer, we must set the ~~PSI~~ to clock mode first, which freezes the counter value in the read buffer. Then we can read the counter using STCR.		To read the buffer, we must set the 9901 to clock mode first, which freezes the counter value in the read buffer. Then we can read the counter using STCR.

	CLR R12		CLR R12
Line 216:		Line 216:
	=== The weird S0 input ===		=== The weird S0 input ===

	There is one peculiarity with the ~~PSI~~. When the input line S0 is set to 1, the clock mode is '''left temporarily''' - until S0 is 0 again, and bit 0 is 1. If bit 0 is 0, this has no effect, as the clock mode is never entered.		There is one peculiarity with the 9901. When the input line S0 is set to 1, the clock mode is '''left temporarily''' - until S0 is 0 again, and bit 0 is 1. If bit 0 is 0, this has no effect, as the clock mode is never entered.

	What is the reason for this?		What is the reason for this?

	TI obviously considered use cases where the ~~PSI~~ remains in clock mode for longer times, while the I/O ports must still be operated. The I/O ports are available on bits 16-31, which means that the S0 input is 1 for these addresses. So when we do a SBO 16, this is not related to the timer value, and thus should control the first I/O port. To allow this, the chip returns to interrupt/port mode for this operation, and when S0 is reset, returns to clock mode.		TI obviously considered use cases where the 9901 remains in clock mode for longer times, while the I/O ports must still be operated. The I/O ports are available on bits 16-31, which means that the S0 input is 1 for these addresses. So when we do a SBO 16, this is not related to the timer value, and thus should control the first I/O port. To allow this, the chip returns to interrupt/port mode for this operation, and when S0 is reset, returns to clock mode.

	In the TI console, the S0-S4 inputs are directly connected with the address bus lines A10-A14. This has a strange side effect: Whenever address bus line A10 changes to 1, the clock mode is left temporarily, and this also happens for ordinary memory accesses.		In the TI console, the S0-S4 inputs are directly connected with the address bus lines A10-A14. This has a strange side effect: Whenever address bus line A10 changes to 1, the clock mode is left temporarily, and this also happens for ordinary memory accesses.
Line 279:		Line 279:
	So can we damage the 9901 in the TI console by a suitable CRU operation? - Luckily not.		So can we damage the 9901 in the TI console by a suitable CRU operation? - Luckily not.

	The reason is the way ~~how~~ TI used the ports on the mainboard. Most of the ports are configured as outputs. Nothing happens when you reset them to inputs.		The reason is the way TI used the ports on the mainboard. Most of the ports are configured as outputs. Nothing happens when you reset them to inputs.

	* The pure interrupt inputs (/INT1 to /INT6) are safe, as they cannot output anything. They have no output driver that could be fried.		* The pure interrupt inputs (/INT1 to /INT6) are safe, as they cannot output anything. They have no output driver that could be fried.

Mizapf: /* Package */

2022-04-23T14:02:17Z

Package

← Older revision		Revision as of 14:02, 23 April 2022
Line 23:		Line 23:
	You can see pins of related functions marked by the same background color.		You can see pins of related functions marked by the same background color.

	* Orange: Interrupt inputs		Orange: Interrupt inputs
	* Red: CRU bit selection (00000 - 11111, i.e. 0-31 decimal)
	* Blue: CRU interface		Red: CRU bit selection (00000 - 11111, i.e. 0-31 decimal)
	* Violet: I/O ports
	* Yellow: Outgoing interrupt and level		Blue: CRU interface

			Violet: I/O ports

			Yellow: Outgoing interrupt and level

	Note that some pins have a double function, or in other words, two functions share the same pin. I will discuss this in the following sections.		Note that some pins have a double function, or in other words, two functions share the same pin. I will discuss this in the following sections.

Mizapf: /* Counter mode */

2022-04-23T13:55:22Z

Counter mode

← Older revision		Revision as of 13:55, 23 April 2022
Line 146:		Line 146:
	Besides the I/O capabilities, the PSI offers a "real-time" clock. This should not be understood as a precise timer with seconds, hundreds of seconds or other but as a countdown timer that is decremented every 64 CPU clock cycles.		Besides the I/O capabilities, the PSI offers a "real-time" clock. This should not be understood as a precise timer with seconds, hundreds of seconds or other but as a countdown timer that is decremented every 64 CPU clock cycles.

	This schematic is taken from the Osborne book, redrawn by me in LibreOffice (and with added Load Buffer).		This schematic is taken from the [[#ref1 \|Osborne book]], redrawn by me in LibreOffice (and with added Load Buffer).

	[[File:Clock9901.png\|550px]]		[[File:Clock9901.png\|550px]]

Mizapf: /* Interrupt mode */

2022-04-23T13:54:48Z

Interrupt mode

← Older revision		Revision as of 13:54, 23 April 2022
Line 88:		Line 88:
	[[File:Int9901.png\|600px]]		[[File:Int9901.png\|600px]]

	This illustration is slightly simplified; there is a latch between each interrupt input and the mask AND gate. This is not relevant for our programming, though. For more details see the ''TMS 9901 Programmable Systems Interface Data Manual''.		This illustration is slightly simplified; there is a latch between each interrupt input and the mask AND gate. This is not relevant for our programming, though. For more details see the [[#ref2 \| TMS 9901 Programmable Systems Interface Data Manual]].

	=== Checking the interrupt inputs ===		=== Checking the interrupt inputs ===

Mizapf: /* Literature */

2022-04-23T13:53:57Z

Literature

← Older revision		Revision as of 13:53, 23 April 2022
Line 293:		Line 293:

	<span id="ref1">[1]</span> Texas Instruments: ''TMS 9901 Programmable Systems Interface Data Manual'', July 1977		<span id="ref1">[1]</span> Texas Instruments: ''TMS 9901 Programmable Systems Interface Data Manual'', July 1977

	<span id="ref2">[2]</span> Adam Osborne, Gerry Kane: ''Osborne 16-Bit Microprocessor Handbook / Includes 2900 Chip Slice Family''. Published by OSBORNE/McGraw-Hill 1975, 1981. ISBN 0-931988-43-8.		<span id="ref2">[2]</span> Adam Osborne, Gerry Kane: ''Osborne 16-Bit Microprocessor Handbook / Includes 2900 Chip Slice Family''. Published by OSBORNE/McGraw-Hill 1975, 1981. ISBN 0-931988-43-8.

Mizapf: /* Literature */

2022-04-23T13:53:41Z

Literature

← Older revision		Revision as of 13:53, 23 April 2022
Line 292:		Line 292:
	== Literature ==		== Literature ==

	<span id="ref1">[1]</span> Adam Osborne, Gerry Kane: ''Osborne 16-Bit Microprocessor Handbook / Includes 2900 Chip Slice Family''. Published by OSBORNE/McGraw-Hill 1975, 1981. ISBN 0-931988-43-8.		<span id="ref1">[1]</span> Texas Instruments: ''TMS 9901 Programmable Systems Interface Data Manual'', July 1977
			<span id="ref2">[2]</span> Adam Osborne, Gerry Kane: ''Osborne 16-Bit Microprocessor Handbook / Includes 2900 Chip Slice Family''. Published by OSBORNE/McGraw-Hill 1975, 1981. ISBN 0-931988-43-8.

Mizapf at 13:51, 23 April 2022

2022-04-23T13:51:39Z

← Older revision		Revision as of 13:51, 23 April 2022
Line 289:		Line 289:

	So we see that resistors are the best way to protect the ports. And we may calm down; we cannot burn the 9901 in the TI console by a bug in our program.		So we see that resistors are the best way to protect the ports. And we may calm down; we cannot burn the 9901 in the TI console by a bug in our program.

			== Literature ==

			<span id="ref1">[1]</span> Adam Osborne, Gerry Kane: ''Osborne 16-Bit Microprocessor Handbook / Includes 2900 Chip Slice Family''. Published by OSBORNE/McGraw-Hill 1975, 1981. ISBN 0-931988-43-8.

Mizapf: /* Arming and disarming interrupts */

2022-04-23T13:45:36Z

Arming and disarming interrupts

← Older revision		Revision as of 13:45, 23 April 2022
Line 138:		Line 138:
	This enables interrupt input /INT2 to cause an /INTREQ when its input changes to 0. In the TI console, /INT2 is connected to the interrupt output of the VDP (video processor). If you want to block interrupts on that input, use SBZ.		This enables interrupt input /INT2 to cause an /INTREQ when its input changes to 0. In the TI console, /INT2 is connected to the interrupt output of the VDP (video processor). If you want to block interrupts on that input, use SBZ.

	It is a common misunderstanding that interrupts can be cleared by using a SBZ on an input. ~~This can, for example, be seen~~ in the popular TI Intern book. Instead, SBZ n simply blocks interrupt input /INTn. In the case of the video processor, it is up to the VDP to clear its interrupt, and this is done by reading its status register.		It is a common misunderstanding that interrupts can be cleared by using a SBZ on an input. I also found this in the popular ''TI Intern'' book. Instead, SBZ n simply blocks interrupt input /INTn. In the case of the video processor, it is up to the VDP to clear its interrupt, and this is done by reading its status register.

			Consequently, you '''cannot''' read the current mask setting of the 9901. What you get from reading are the input levels of the pins. So if you plan to change the mask bits temporarily, be aware that you cannot ask the 9901 to give you the current setting which you want to restore later. You will have to find out by another way.

	== Counter mode ==		== Counter mode ==

Mizapf: /* Input/Output port operation */

2022-04-23T13:40:37Z

Input/Output port operation

← Older revision		Revision as of 13:40, 23 April 2022
Line 47:		Line 47:
	JEQ P2ACT		JEQ P2ACT

	TB copies the bit at the given CRU address into the Equal bit of the status register. JEQ will jump to the location when this input has a high level. The maximum input current is 100 µA. You should protect the input with a resistor; see below for a more detailed discussion.		TB copies the bit at the given CRU address into the Equal bit of the status register. JEQ will jump to the location when this input has a high level. The maximum input current is 100 µA. You should protect the input with a resistor; [[#Safety_precautions \| see below]] for a more detailed discussion.

	If you want to read all 16 ports, use the STCR instruction:		If you want to read all 16 ports, use the STCR instruction:

Mizapf: /* Input/Output port operation */

2022-04-23T13:39:53Z

Input/Output port operation

← Older revision		Revision as of 13:39, 23 April 2022
Line 56:		Line 56:
	Note that the CRU base address in R12 advances in steps of 2, so bit 16 is on address 32. Also, for reading 16 bits, you must specify a count of 0.		Note that the CRU base address in R12 advances in steps of 2, so bit 16 is on address 32. Also, for reading 16 bits, you must specify a count of 0.

	The 9901 offers some more inputs than the 16 ports; we can use the interrupt inputs as well. More about that can be found in the section about the [[#~~interrupt_mode~~\| interrupt mode]].		The 9901 offers some more inputs than the 16 ports; we can use the interrupt inputs as well. More about that can be found in the section about the [[#Interrupt_mode\| interrupt mode]].

	=== Px port as output ===		=== Px port as output ===