Difference between revisions of "Geneve GPL Interpreter"
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For different speeds different kinds of RAM (DRAM vs. SRAM) are used. The ROMPAGE feature sets the 4000-5FFF | For different speeds different kinds of RAM (DRAM vs. SRAM) are used. The ROMPAGE feature sets the mapper address 8002 (4000-5FFF) to BA, which points to the address space of the peripheral card in the box; normally, page 07 is set which contains the GeneveOS Master DSR. | ||
The cartridge ROM (6000-7FFF) is always mapped as page 36, while the second ROM page is 37; this is fixed inside the Gate Array in GPL mode, so changes to the settings at 8003 have no effect. The GROM pages are 38-3F. Page 03 must stay mapped to C000 (mapper address 8006) to enable GROM/GRAM and sound access; changing this values inhibits the access. | |||
== Speed selection == | == Speed selection == | ||
Latest revision as of 17:54, 10 April 2021
Mapping
For Speed 5 and MDOS DSR:
| Page for 0000-1FFF | Page for 2000-3FFF | Page for 4000-5FFF | Page for 6000-7FFF | Page for 8000-9FFF | Page for A000-BFFF | Page for C000-DFFF | Page for E000-FFFF |
|---|---|---|---|---|---|---|---|
| EC | ED | 07 | 36 | EE | EF | 03 | 35 |
For different speeds different kinds of RAM (DRAM vs. SRAM) are used. The ROMPAGE feature sets the mapper address 8002 (4000-5FFF) to BA, which points to the address space of the peripheral card in the box; normally, page 07 is set which contains the GeneveOS Master DSR.
The cartridge ROM (6000-7FFF) is always mapped as page 36, while the second ROM page is 37; this is fixed inside the Gate Array in GPL mode, so changes to the settings at 8003 have no effect. The GROM pages are 38-3F. Page 03 must stay mapped to C000 (mapper address 8006) to enable GROM/GRAM and sound access; changing this values inhibits the access.
Speed selection
The GPL Interpreter allows for selecting the execution speed. Five speeds are selectable. The speed is determined by these settings:
| Speed | Video waitstates | Extra waitstates | Page for 0000-1FFF | Page for 8000-9FFF |
|---|---|---|---|---|
| 1 | x | x | EC | 34 |
| 2 | x | - | 33 | 34 |
| 3 | x | - | EC | 34 |
| 4 | x | - | 33 | EE |
| 5 | x | - | EC | EE |
The memory pages EC, ED, EE, and EF are SRAM pages with 0 waitstate access. Other pages are DRAM pages with one waitstate. Thus, the speed is controlled by waitstates in the GPL interpreter (locations 0000-1FFF) and in the PAD RAM (8300-83FF), which is not the high speed on-chip RAM of the TMS9995 processor (which is always located at F000, regardless of the mapper value).