Difference between revisions of "Geneve logical memory map"
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The logical address map determines which devices or memory areas appear in the logical address space. These are the addresses as seen from the CPU or the program that is run, but they need not correspond to the same physical address at all times. The correspondence is provided by the [[Geneve paged memory organization | mapper]]. | The logical address map determines which devices or memory areas appear in the logical address space. These are the addresses as seen from the CPU or the program that is run, but they need not correspond to the same physical address at all times. The correspondence is provided by the [[Geneve paged memory organization | mapper]]. | ||
The [[Geneve Memory Management Functions | memory management ]] in Native mode is supported by a XOP call. | |||
== Native mode == | == Native mode == | ||
| Line 32: | Line 34: | ||
|- | |- | ||
! F000 | ! F000 | ||
| rowspan="1" class="freeon" | On-chip memory | | rowspan="1" class="freeon" | On-chip memory 252 bytes | ||
| rowspan="1" class="descr" | Hides mapped page | | rowspan="1" class="descr" | Hides mapped page up to F0FB (see below) | ||
|- | |- | ||
! F100 | ! F100 | ||
| rowspan="1" | Video ports | | rowspan="1" | Video ports | ||
| class="descr" | See below | | class="descr" | See below | ||
|- | |- | ||
! F110 | ! F110 | ||
| [[Geneve paged memory organization | Mapper ]] | | [[Geneve paged memory organization | Mapper ]] | ||
| class="descr" | See link | | class="descr" | See link | ||
|- | |||
! F118 | |||
| [[Geneve keyboard control | Keyboard ]] | |||
| class="descr" | Single address F118 with 8 mirrors | |||
|- | |- | ||
! F120 | ! F120 | ||
| Sound chip | | Sound chip | ||
| class="descr" | Single address F120 with 8 mirrors on even addresses | |||
|- | |- | ||
! F130 | ! F130 | ||
| Clock chip | | [[Real-time clock | Clock chip]] | ||
|- | |- | ||
! F140 | ! F140 | ||
| Line 69: | Line 73: | ||
|- | |- | ||
|} | |} | ||
=== On-chip memory === | |||
The on-chip memory of the TMS9995 consists of the address range F000-F0FB and FFFC-FFFF, 256 bytes. The latter four bytes are used for the NMI vector (formerly known as LOAD interrupt vector). The word at FFFA is the decrementer; it may be used as a memory storage when the decrementer is halted. | |||
The memory area is equipped with SRAM at 0 wait states, with full 16 bit access. It is the fastest RAM in the system. Hence, register workspaces should make good use of this area. In that respect, it resembles the Scratch pad RAM of the TI-99/4A. | |||
The on-chip RAM cannot be mapped in or out; it is always present at the specified logical addresses. According to the 9995 specifications, on-chip memory accesses are visible outside; the external address bus is set (only for the even address, as these are full 16-bit accesses), and unspecified data is output on the external data bus on write operations. This means that the hidden RAM is overwritten. | |||
=== Video ports === | === Video ports === | ||
Decoding: 1111 0001 0000 xpp0 (pp = port number; x = don't care) | |||
Addresses are mirrored at position+8 (F100 = F108,...) | |||
{| class="memory" | {| class="memory" | ||
! | ! | ||
! Read | ! class="mmap" | Read | ||
! Write | ! class="mmap" | Write | ||
|- | |- | ||
! F100 (Port 0) | ! F100 (Port 0) | ||
| Line 97: | Line 113: | ||
The GPL mode is the compatibility mode, which is provided to run TI-99/4A programs. | The GPL mode is the compatibility mode, which is provided to run TI-99/4A programs. | ||
=== Memory map === | |||
{| class="memory" | {| class="memory" | ||
| Line 125: | Line 143: | ||
|- | |- | ||
! 8008 | ! 8008 | ||
| Keyboard | | [[Geneve keyboard control | Keyboard ]] | ||
|- | |- | ||
! 8010 | ! 8010 | ||
| Clock chip | | [[Real-time clock | Clock chip]] | ||
|- | |- | ||
! 8020 | ! 8020 | ||
| rowspan="2" class="free" | Free space | | rowspan="2" class="free" | Free space 992 bytes | ||
| class="descr" | Also includes the "PAD RAM" (16-bit RAM of the TI-99/4A) | | class="descr" | Also includes the "PAD RAM" (16-bit RAM of the TI-99/4A) | ||
|- | |- | ||
| Line 155: | Line 173: | ||
|- | |- | ||
! A000 | ! A000 | ||
| rowspan="3" class="free" | Free space | | rowspan="3" class="free" | Free space 20 KiB | ||
|- | |- | ||
! C000 | ! C000 | ||
| Line 163: | Line 181: | ||
! F000 | ! F000 | ||
| rowspan="1" class="freeon" | On-chip memory | | rowspan="1" class="freeon" | On-chip memory | ||
| rowspan="1" class="descr" | Hides mapped page | | rowspan="1" class="descr" | Hides mapped page up to F0FB (see above) | ||
|- | |- | ||
! | ! F0FC | ||
| class="free" | Free space | | class="free" | Free space 3838 bytes | ||
|- | |- | ||
! FFFA | ! FFFA | ||
| Line 177: | Line 195: | ||
|- | |- | ||
|} | |} | ||
=== Video ports === | |||
Decoding: 1000 1wxx xxxx xpp0 (pp = port number; x = don't care; w = write) | |||
Addresses are mirrored 64 times (8800 = 8810 = 8820 = ... 8BF0) | |||
{| class="memory" | |||
! | |||
! class="mmap" | Read | |||
! class="mmap" | Write | |||
|- | |||
! 8800 (Port 0) | |||
| class="mmap" | VRAM | |||
| - | |||
|- | |||
! 8C00 (Port 0) | |||
| - | |||
| class="mmap" | VRAM | |||
|- | |||
! 8802 (Port 1) | |||
| class="mmap" | Status register | |||
| - | |||
|- | |||
! 8C02 (Port 1) | |||
| - | |||
| class="mmap" | Address counter or video register | |||
|- | |||
! 8C04 (Port 2) | |||
| - | |||
| class="mmap" | Palette register | |||
|- | |||
! 8C06 (Port 3) | |||
| - | |||
| class="mmap" | Indirect video register access | |||
|} | |||
[[Category:Geneve]] | |||
[[Category:Hardware]] | |||
Latest revision as of 20:59, 28 January 2021
The logical address map determines which devices or memory areas appear in the logical address space. These are the addresses as seen from the CPU or the program that is run, but they need not correspond to the same physical address at all times. The correspondence is provided by the mapper.
The memory management in Native mode is supported by a XOP call.
Native mode
The native mode is also called MDOS mode. It is the mode which the Geneve initially boots to, typically with white letters on dark blue, and 80 column display.
Memory map
| 0000 | Reserved | Operating system |
|---|---|---|
| 0400 | Free space | Onboard memory or expansion |
| 2000 | ||
| 4000 | ||
| 6000 | ||
| 8000 | ||
| A000 | ||
| C000 | ||
| E000 | ||
| F000 | On-chip memory 252 bytes | Hides mapped page up to F0FB (see below) |
| F100 | Video ports | See below |
| F110 | Mapper | See link |
| F118 | Keyboard | Single address F118 with 8 mirrors |
| F120 | Sound chip | Single address F120 with 8 mirrors on even addresses |
| F130 | Clock chip | |
| F140 | Free space | Onboard memory or expansion |
| F800 | ||
| FFF8 | ||
| FFFA | Decrementer | |
| FFFC | NMI vector | |
| FFFE |
On-chip memory
The on-chip memory of the TMS9995 consists of the address range F000-F0FB and FFFC-FFFF, 256 bytes. The latter four bytes are used for the NMI vector (formerly known as LOAD interrupt vector). The word at FFFA is the decrementer; it may be used as a memory storage when the decrementer is halted.
The memory area is equipped with SRAM at 0 wait states, with full 16 bit access. It is the fastest RAM in the system. Hence, register workspaces should make good use of this area. In that respect, it resembles the Scratch pad RAM of the TI-99/4A.
The on-chip RAM cannot be mapped in or out; it is always present at the specified logical addresses. According to the 9995 specifications, on-chip memory accesses are visible outside; the external address bus is set (only for the even address, as these are full 16-bit accesses), and unspecified data is output on the external data bus on write operations. This means that the hidden RAM is overwritten.
Video ports
Decoding: 1111 0001 0000 xpp0 (pp = port number; x = don't care)
Addresses are mirrored at position+8 (F100 = F108,...)
| Read | Write | |
|---|---|---|
| F100 (Port 0) | VRAM | VRAM |
| F102 (Port 1) | Status register | Address counter or video register |
| F104 (Port 2) | - | Palette register |
| F106 (Port 3) | - | Indirect video register access |
GPL mode
The GPL mode is the compatibility mode, which is provided to run TI-99/4A programs.
Memory map
| 0000 | GPL interpreter | Operating system |
|---|---|---|
| 2000 | Free space 8 KiB | Onboard memory or expansion |
| 3000 | ||
| 3FFE | ||
| 4000 | DSR space | Normally used by the GeneveOS DSR |
| 6000 | Cartridge ROM contents | Loaded from disk |
| 8000 | Mapper | See link |
| 8008 | Keyboard | |
| 8010 | Clock chip | |
| 8020 | Free space 992 bytes | Also includes the "PAD RAM" (16-bit RAM of the TI-99/4A) |
| 8300 | Here, its speed depends on SRAM or DRAM mapping | |
| 8400 | Sound chip | |
| 8600 | External bus | Any device in the PEB that maps to this address |
| 8800 | Video ports | |
| 9000 | Speech synthesizer | if plugged into the PEB |
| 9800 | GRAM | |
| A000 | Free space 20 KiB | |
| C000 | ||
| E000 | ||
| F000 | On-chip memory | Hides mapped page up to F0FB (see above) |
| F0FC | Free space 3838 bytes | |
| FFFA | Decrementer | |
| FFFC | NMI vector | |
| FFFE |
Video ports
Decoding: 1000 1wxx xxxx xpp0 (pp = port number; x = don't care; w = write)
Addresses are mirrored 64 times (8800 = 8810 = 8820 = ... 8BF0)
| Read | Write | |
|---|---|---|
| 8800 (Port 0) | VRAM | - |
| 8C00 (Port 0) | - | VRAM |
| 8802 (Port 1) | Status register | - |
| 8C02 (Port 1) | - | Address counter or video register |
| 8C04 (Port 2) | - | Palette register |
| 8C06 (Port 3) | - | Indirect video register access |