Benchmarking

Using the on-board real-time clock (RTC) we can do a lot of interesting tests on the Geneve, in its MDOS and GPL mode.

Timer main program

TODO

Determining the video interrupt rate

* Wait in a loop until the desired number of
* interrupts have occured

START  LIMI 0
       CLR  R12
       SBO  2               enable VDP interrupt propagation through 9901

       LI   R0,>8170        VReg 1 contains a flag to enable vertical sync interrupt
       SWPB R0
       MOVB R0,@>F102
       SWPB R0
       MOVB R0,@>F102

       LI   R0,>8980        VReg 9 contains flags to set 192/212 lines, NTSC/PAL, interlace/non-interlace
       SWPB R0
       MOVB R0,@>F102
       SWPB R0
       MOVB R0,@>F102

       MOV  @>0004,R6       Save INT2 vector to R6/R7
       MOV  @>0006,R7 

       LI   R0,>F040        Set our own interrupt routine at INT2
       MOV  R0,@>0004
       LI   R0,INTR
       MOV  R0,@>0006 

* We set our counter to 1000 interrupts
       LI   R3,1000
       MOV  R3,@ITER

* Arm the interrupts
       LIMI 2

* ... and wait in a loop until the counter is zero
T012   MOV  @ITER,R0
       JNE  T012

* Block the interrupts again
       LIMI 0
       MOV  R6,@>0004         Restore the vector
       MOV  R7,@>0006 

T01E   RT

This is the interrupt routine which we have to install:

ITER   DATA 0      Counter

* Start of the routine
INTR   LIMI 0      Block all interrupts (see below, 1)

* Read the status registers. This will clear the flags. (2)
* One of the flags is in SREG1
       BL   @GETREG
       DATA 1
       BL   @GETREG
       DATA 0
       SLA  R0,1         Is the leftmost flag set (VSYNC)?
       JNC  SKIP         If not, skip the DEC command
       DEC  @ITER        Decrease our counter 
SKIP   RTWP

* Routine to read a given status register into R0
* Register number must be in data line (LSB) 

GETREG MOV  *R11+,R0
       ORI  R0,>8F00
       SWPB R0
       MOVB R0,@>F102
       SWPB R0
       MOVB R0,@>F102
       CLR  R0
       NOP
       MOVB @>F102,R0
       RT

Comments:

(1) We have to disable the interrupts here. The routine above has set the mask to 0002, which enables interrupts from other sources as well. If we do not block the interrupts, another interrupt request may interrupt this handler, and we will lose the return vector. The RTWP command at the end will restore the interrupt mask.

(2) We must clear the flag which caused the interrupt. Unless cleared, the INT line from the VDP will stay low (active) and will re-trigger the interrupt. So the first thing to do in the interrupt handler is to clear the origin of the interrupt.

Result of the video benchmark

Using the RTC we can determine the time which passed between the first and the 1000th interrupt:

• NTSC set (video register 9): 16.67 s
• PAL set (also in reg 9): 20.0 s

Accordingly, we get 60 Hz for the NTSC and 50 Hz for the PAL setting. The timing is not affected by the number of display lines (192 or 212) and not by interlace mode (on or off).