Difference between revisions of "Geneve physical memory map"

From Ninerpedia
Jump to navigation Jump to search
(Created page with "The physical memory map declares which physical addresses are used to access memory regions or devices.")
 
Line 1: Line 1:
The physical memory map declares which physical addresses are used to access memory regions or devices.
The physical memory map declares which physical addresses are used to access memory regions or devices.
== Native mode ==
=== Memory map ===
{| class="memory"
!
! Banks
! Region
!
|-
! 000000
| class="bank" | 00-3F
| 512 KiB On-board DRAM
| class="descr" | Slow RAM (1 ws)
|-
! 080000
| class="bank" | 40-7F
| 512 KiB On-board DRAM expansion
| class="descr" | Allocated, but technically infeasible (no sockets or signal lines)
|-
! 100000
| class="bank" | 80-B7
| 448 KiB P-Box space
| class="descr" | May be used my MEMEX card
|-
! 170000
| class="bank" | B8-BF
| 64 KiB P-Box space
| class="descr" | Used by current expansion cards
|-
! 180000
| class="bank" | C0-E7
| Future expansion
| class="descr" | SRAM expansion in the P-Box
|-
! 1D0000
| class="bank" | E8-EB
| 32 KiB On-board SRAM expansion
| class="descr" | Soldered on top of the existing 32 KiB chip
|-
! 1D8000
| class="bank" | EC-EF
| 32 KiB On-board SRAM
| class="descr" | Original SRAM memory (0 ws)
|-
! 1E0000
| class="bank" | F0-FF
| 128 KiB Boot EPROM
| class="descr" | Originally, only 16 KiB installed at F0,F1; mirrored
|}
=== Boot EPROM space ===
The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the [[PFM]].
On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.
== GPL mode ==
{| class="memory"
!
! Banks
! Region
|-
! 000000
| class="bank" | 00-35
| 432 KiB On-board DRAM
| class="descr" | Slow RAM (1 ws)
|-
! 06C000
| class="bank" | 36
| 8 KiB Cartridge ROM space (bank 1)
| class="descr" | First bank of cartridge (Extended Basic style)
|-
! 06E000
| class="bank" | 37
| 8 KiB Cartridge ROM space (bank 2)
| class="descr" | Second bank of cartridge (Extended Basic style)
|-
! 070000
| class="bank" | 38-3F
| 64 KiB GRAM Cartridge space
| class="descr" | [[Geneve paged memory organization | Map byte 06]] must be set to 0x03 to enable GRAM
|-
! 080000
| class="bank" | 40-7F
| 512 KiB On-board DRAM expansion
| class="descr" | Allocated, but technically infeasible (no sockets or signal lines)
|-
! 100000
| class="bank" | 80-B7
| 448 KiB P-Box space
| class="descr" | May be used my MEMEX card
|-
! 170000
| class="bank" | B8-BF
| 64 KiB P-Box space
| class="descr" | Used by current expansion cards
|-
! 180000
| class="bank" | C0-E7
| Future expansion
| class="descr" | SRAM expansion in the P-Box
|-
! 1D0000
| class="bank" | E8-EB
| 32 KiB On-board SRAM expansion
| class="descr" | Soldered on top of the existing 32 KiB chip
|-
! 1D8000
| class="bank" | EC-EF
| 32 KiB On-board SRAM
| class="descr" | Original SRAM memory (0 ws)
|-
! 1E0000
| class="bank" | F0-FF
| 128 KiB Boot EPROM
| class="descr" | Originally, only 16 KiB installed at F0,F1; mirrored
|}
== Genmod ==
The Genmod (Geneve modification) can be run in two modes, selectable by a switch. The TI mode activates the on-board slow DRAM, which is required to run the GPL mode. The reason is that the Gate array maps the GROM accesses to the DRAM on the board, which cannot be changed to the external RAM.
=== TI mode ===
{| class="memory"
!
! Banks
! Region
!
|-
! 000000
| class="bank" | 00-35
| 432 KiB On-board DRAM
| class="descr" | Slow RAM (1 ws)
|-
! 06C000
| class="bank" | 36
| 8 KiB Cartridge ROM space (bank 1)
| class="descr" | First bank of cartridge (Extended Basic style)
|-
! 06E000
| class="bank" | 37
| 8 KiB Cartridge ROM space (bank 2)
| class="descr" | Second bank of cartridge (Extended Basic style)
|-
! 070000
| class="bank" | 38-3F
| 64 KiB GRAM Cartridge space
| class="descr" | [[Geneve paged memory organization | Map byte 06]] must be set to 0x03 to enable GRAM
|--
! 080000
| class="bank" | 40-EF
| 1408 KiB P-Box memory expansion (MEMEX)
| class="descr" | SRAM (0 ws)
|-
! 1E0000
| class="bank" | F0-FF
| 128 KiB Boot EPROM
| class="descr" | Originally, only 16 KiB installed at F0,F1; mirrored
|}
=== Non-TI mode ===
{| class="memory"
!
! Banks
! Region
!
|-
! 000000
| class="bank" | 00-EF
| 1920 P-Box memory expansion (MEMEX)
| class="descr" | SRAM (0 ws)
|-
! 1E0000
| class="bank" | F0-FF
| 128 KiB Boot EPROM
| class="descr" | Originally, only 16 KiB installed at F0,F1; mirrored
|}

Revision as of 12:18, 27 January 2021

The physical memory map declares which physical addresses are used to access memory regions or devices.

Native mode

Memory map

Banks Region
000000 00-3F 512 KiB On-board DRAM Slow RAM (1 ws)
080000 40-7F 512 KiB On-board DRAM expansion Allocated, but technically infeasible (no sockets or signal lines)
100000 80-B7 448 KiB P-Box space May be used my MEMEX card
170000 B8-BF 64 KiB P-Box space Used by current expansion cards
180000 C0-E7 Future expansion SRAM expansion in the P-Box
1D0000 E8-EB 32 KiB On-board SRAM expansion Soldered on top of the existing 32 KiB chip
1D8000 EC-EF 32 KiB On-board SRAM Original SRAM memory (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored

Boot EPROM space

The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the PFM.

On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.

GPL mode

Banks Region
000000 00-35 432 KiB On-board DRAM Slow RAM (1 ws)
06C000 36 8 KiB Cartridge ROM space (bank 1) First bank of cartridge (Extended Basic style)
06E000 37 8 KiB Cartridge ROM space (bank 2) Second bank of cartridge (Extended Basic style)
070000 38-3F 64 KiB GRAM Cartridge space Map byte 06 must be set to 0x03 to enable GRAM
080000 40-7F 512 KiB On-board DRAM expansion Allocated, but technically infeasible (no sockets or signal lines)
100000 80-B7 448 KiB P-Box space May be used my MEMEX card
170000 B8-BF 64 KiB P-Box space Used by current expansion cards
180000 C0-E7 Future expansion SRAM expansion in the P-Box
1D0000 E8-EB 32 KiB On-board SRAM expansion Soldered on top of the existing 32 KiB chip
1D8000 EC-EF 32 KiB On-board SRAM Original SRAM memory (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored

Genmod

The Genmod (Geneve modification) can be run in two modes, selectable by a switch. The TI mode activates the on-board slow DRAM, which is required to run the GPL mode. The reason is that the Gate array maps the GROM accesses to the DRAM on the board, which cannot be changed to the external RAM.

TI mode

Banks Region
000000 00-35 432 KiB On-board DRAM Slow RAM (1 ws)
06C000 36 8 KiB Cartridge ROM space (bank 1) First bank of cartridge (Extended Basic style)
06E000 37 8 KiB Cartridge ROM space (bank 2) Second bank of cartridge (Extended Basic style)
070000 38-3F 64 KiB GRAM Cartridge space Map byte 06 must be set to 0x03 to enable GRAM
080000 40-EF 1408 KiB P-Box memory expansion (MEMEX) SRAM (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored

Non-TI mode

Banks Region
000000 00-EF 1920 P-Box memory expansion (MEMEX) SRAM (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored
Retrieved from "http://www.ninerpedia.org/index.php?title=Geneve_physical_memory_map&oldid=50501"