Geneve CRU definitions
Definitions
CRU bits may be tested with the TB command, with the base address in R12. The bit is copied to the EQ flag of the status register so that a JEQ will cause a branch whenever the bit is set.
The bits of the 9901 are tested in positive logic, which means that a low value on the pin will make a TB yield EQ=0, and a high value on the pin makes EQ=1. The signals on the pins may show negative logic themselves. That is, if the joystick button is pressed, a low value is put on the /INT3 input (bit 3), and a TB 3 will make EQ=0, while a not pressed button would be EQ=1.
TMS9901 lines may be configured as inputs (in), outputs (out), and the first 16 addresses may be configured as interrupt inputs (int), triggering an outgoing interrupt if the mask is set to 1 for the respective input.
(/signal means negative logic)
| TMS 9901 | ||
| 0002 | int | /INTA (P-Box, pin 17) |
| 0004 | int | /V9938 INT |
| 0006 | in | /Joystick button |
| 0008 | in | /Joystick left |
| 000a | in | /Joystick right |
| 000c | in | /Joystick down |
| 000e | in | /Joystick up |
| 0010 | int | /Keyboard Interrupt |
| 0012 | in | always H, mirrors 003a |
| 0014 | in | Mouse button, mirrors 0038 |
| 0016 | in | - |
| 0018 | in | /INTB (mirrors 0034) |
| 001a | in | - |
| 001c | in | - |
| 001e | in | - |
| 0020 | out | RESET (P-Box, pin 6 (inverted)) |
| 0022 | out | /V9938 reset |
| 0024 | out | Joystick select |
| 0026 | - | - |
| 0028 | - | - |
| 002a | - | - |
| 002c | out | /Keyboard reset (neg. logic?) |
| 002e | out | PAL pin 5 (/VDP wait states?) |
| 0030 | - | - |
| 0032 | out | PAL pin 19 (System clock speed?) |
| 0034 | in | /INTB (P-Box pin 18) |
| 0036 | in | Real-time clock interrupt (/?) |
| 0038 | in | /Mouse button 3 |
| 003a | in | H |
| 003c | in | /Keyboard interrupt (mirrors 0010, no int) |
| 003e | in | /Joystick up (mirrors 000e) |
| Special | |
| 13c0-13fe | Single step |
| TMS9995 | |
| 1ee0 | Decrementer in event counter mode (0=in timer mode) |
| 1ee2 | Enable decrementer |
| 1ee4 | Interrupt level 1 latch |
| 1ee6 | Interrupt level 2 latch |
| 1ee8 | Interrupt level 4 latch |
| 1eea-1eee | not used |
| 1ef0 | Keyboard clock enable |
| 1ef2 | Clear keyboard input register |
| 1ef4 | Geneve mode (/TI mode) |
| 1ef6 | Direct mode (/Mapper mode) |
| 1ef8 | Cartridge rom size (1=8 KiB, 0=16 Kib) |
| 1efa | /Protect 6xxx |
| 1efc | /Protect 7xxx |
| 1efe | /Add wait state per memory cycle |
| 1fda | Macro Instruction Detect |
The MID flag is set whenever the CPU encounters an unknown opcode. This (together with the interrupt) may be used to implement new "commands" on the application level.
Usage
As always, CRU bits are queried and set with special commands. Bits are addressed as offsets to a base address which is stored in Workspace Register 12 (R12). The base address is stored in bits 3-14, so the R12 value is twice as high as the absolute bit address. (Note that bit 15 cannot be used since A15 and CRUOUT share the same line.) Base addresses are commonly noted as register 12 values.
Turn on Geneve mode:
LI R12,>1EF4 SBO 0
or, equivalently
LI R12,>1EE0 SBO 10
since 0x1ee0 + 10*2 = 0x1ee0 + 0x14
(bit numbers are often given in decimal notation)
The LDCR and STCR commands are used to write or read multiple CRU bits. The base address is automatically incremented for each bit transfer. Bit transfers begin at the least significant bit. Note that it is relevant whether less than 9 bits are transferred: If less, the memory location is treated as a byte address, if more, as a word address.
LI R12,>0006 STCR R0,5
reads the five joystick lines, storing the bits in the least significant five bits of the high byte of R0, with bit 3 at the right.
| x | x | x | up | down | right | left | but | x | x | x | x | x | x | x | x |
If we had transferred 9 bits, all bits as shown above are shifted to the right by 8 positions (starting at the very right bit).
LI R12,>1EF0 LI R1,>f100 * binary: 11110001 LCDR R1,8
This enables the keyboard clock, not clearing the input register, activating TI mode and mapping, cartridges have 8K, no write protection to 6xxx and 7xxx, and no wait states.