Geneve keyboard control

The Geneve uses a MF1 keyboard (PC-XT). Access to the keyboard is implemented as follows:

Keyboard interface

Shift register

In MDOS mode, the address F118 is used to access the 8-bit shift register in the Gate array which stores the most recent scancode. In TI mode, the address is 8008. The address is not fully decoded; the rightmost three bits are ignored (F118 is the same as F11F).

The shift register is readable throughout the receive period of the scancode; this means you can watch the scancode coming in, shifted from left to right. This also means that you must make use of the available flag to find out whether the shift register contains the full scancode.

Available flag

The bit at CRU address 0010 (or bit 8 at base 0) is set to 1 by default. The interrupt inputs at the 9901 are all negative logic, so we need a 0 to trigger an interrupt.

It is set to 0 when a scancode is available in the shift register at F118. The input is configured to raise an interrupt which will make MDOS read the scancode and put it in a buffer, unless interrupts are masked out (using LIMI).

The bit is reset to 1 with the next SBZ on the control bit 1.

Control bit 0

The bit at CRU address 1EF0 has two functions:

• When set to 0 (SBZ), the keyboard clock is turned off. All following keystrokes are buffered in the keyboard and are not propagated to the Gate Array.
• When set to 1 (SBO), a reset occurs (only if the previous state was 0; otherwise no effect). This means the states of CapsLock, NumLock, and ScrollLock are set to off, the keyboard performs a self-test, clears the scancode buffer, and sends a >AA code to the computer. This scancode is transmitted as any other scancode, i.e. we have to check the available flag before getting it from the shift register.

Control bit 1

The bit at CRU address 1EF2 also has two functions:

• When set to 0 (SBZ), the shift register is cleared, the available flag is set to 1, and the clock line is enabled. This means the keyboard will now begin to send its buffered scancodes. The shift register is locked to 0, and any incoming scancode will be lost.
• When set to 1 (SBO), the shift register is set to receive. The next incoming scancode will be read into the shift register. Scancodes are transmitted LSB first, so the shift register is loaded from the left. When the complete scancode has been received, the available flag is set to 0, and the clock line is disabled.

Scancode reception is done in the background, without program control. The shift register will accept a scan code at any time after the SBO. This means that the shift register should be checked whether it contains a scancode that has been received in the meantime before setting the control bit 1 to 0, since this will wipe the shift register.